
/*------------------- include --------------------*/

/*---------------------------------------------*/



module tb_cbb_dpram; 

reg clk ; 

reg rst_n;          //复位信号


//生成时钟
parameter NCLK = 1000/25.0;  // 25MHz
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb_cbb_dpram);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end


reg [7:0] waddr , raddr , din ;
reg we , re ;
cbb_tiny_fifo#(
    .DATA_WIDTH (8)   ,  //数据宽度
    .ADDR_WIDTH (3)   ,  // fifo 存储 (1<<ADDR_WIDTH) -1  个数据 
    .ENABLE_RESET( 1) ,  // 1 生成 复位电路
    .ASYNC_OUT( 0 )      // 1 输出异步于时钟(re有效则输出有效) 
) u_tiny_fifo (
    .clk(clk) , 
    .reset(~rst_n) , 
    .we(we) , 
    .re(re) , 
    .i_data(din) , 
    .o_data() , 
    .o_valid() , 
    .full() , 
    .empty()   
);



initial begin
    $display(" -------- psm sim ----------");
    rst_n = 0;
    din = 0;
    we = 0 ; 
    re = 0 ;
    waddr = 0 ; 
    raddr = 0 ;
    repeat(2) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(10) @(posedge clk) ;

    // repeat(1) begin
    //     @(posedge clk) begin we <= 1 ; din <= din+1;  re <= 0 ;  end 
    //     @(posedge clk) begin we <= 0 ; din <= din;  re <= 1  ; end
    // end 

    repeat(7) begin
        @(posedge clk) begin 
            we <= 1 ; din <= din+1;  re <= 0 ;  
            $display("Write:%d",din+1) ;
        end  
    end 

    repeat(2) @(posedge clk) begin we <= 1'b0 ; end   

    repeat(10) begin
        @(posedge clk) begin 
            we <= 0 ; 
            if(!u_tiny_fifo.empty) begin 
                re <= 1  ;
            end else re <= 1'b0; 

            if(u_tiny_fifo.o_valid) $display("Read :%d",u_tiny_fifo.o_data) ;
        end
    end 


    @(posedge clk) begin we <= 0 ; din <= 8'hz; re <= 0 ;  end
    repeat(10) @(posedge clk) ;
    $display("done!");
	$dumpflush;
	$finish;
	$stop;	
end


// task push(input [7:0] d);
//     // input [7:0] d ; 
//     @(posedge clk) begin we <= 1 ; din <= d;   end
// endtask 



endmodule